xe2x80x9cA Novel Method of Defining A Buried Stack Capacitor Structure For A One Transistor SRAM Cellxe2x80x9d, by W. C. Chen et al, of Taiwan Semiconductor Manufacturing Corporation, filed on Dec. 12, 2001, Ser. No. 10/020,753, U.S. Pat. No. 6,420,226 assigned to a common assignee.
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a buried stack capacitor structure for a static random access memory (SRAM), cell.
(2) Description of Prior Art
SRAM cells have in the past been fabricated using six transistors, usually comprised of four N channel, metal oxide semiconductor field effect transistor (MOSFET), devices, and of two P channel MOSFET devices. However to reduce processing costs the semiconductor industry has been attempting to fabricate smaller chips, allowing a greater number of smaller semiconductor chips to be obtained from a specific size starting substrate thus reducing the processing cost of a specific semiconductor chip. The smaller semiconductor chips are designed to offer device densities equal to, or greater than counterpart larger semiconductor chips. However the use of smaller chips for SRAM technology create problems when attempting to place six transistors on the smaller semiconductor chip. Therefore SRAM designs have focused on pseudo type, or a one transistor, 1 T SRAM cell, comprised with a single metal oxide semiconductor field effect transistor (MOSFET) device, and a single capacitor structure. This configuration, featuring a single transistor and a single capacitor structure, provides the same function as the six transistor design, however requiring less space and thus fulfilling the objective of constructing smaller semiconductor chips.
This invention will describe a novel process sequence in which the 1 T SRAM cell is fabricated using a buried stacked capacitor structure, with the buried stacked capacitor structure option requiring less space than a counterpart trench type, or a stacked type capacitor structure. In addition the integrated process described in this invention will feature unique process sequences targeted at eliminating silicon damage, and eliminating polysilicon stringer formation, which can occur during buried stack capacitor fabrication. Prior art such as Arnold, in U.S. Pat. No. 6,150,210, as well as Huang, in U.S. Pat. No. 6,251,726, describe processes for integrating the fabrication of capacitor structures in dynamic random access memory (DRAM) cells. However those prior arts do not describe the novel process features highlighted in this present invention directed at the fabrication of a buried stack capacitor structure, as an component of a 1 T SRAM cell, featuring process sequences designed to eliminate silicon damage and polysilicon stringers which can occur during the integrated process sequence.
It is an object of this invention to fabricate a buried stack capacitor structure for use in memory cells, such as a static random access memory (SRAM), cell.
It is another object of this invention to define a self-aligned opening for the buried stacked capacitor structure, via use of selective dry etching, and selective wet etching procedures, with the selective etch procedure preventing damage to regions of the semiconductor substrate exposed at the conclusion of the self-aligned opening.
It is still another object of this invention to form an implanted well region for logic applications early in process sequence, after formation of a shallow trench isolation region and after a subsequently formed sacrificial silicon dioxide layer, to avoid damage to capacitor dielectric layer which can occur if well implant procedure is performed after capacitor formation.
It is still yet another object of this invention to use a disposable silicon oxide layer, and a chemical mechanical polishing (CMP) procedure for planarization purposes, allowing definition of a storage node structure, obtained via deposition of, and patterning of a polysilicon layer, to be accomplished without forming polysilicon stringers between the subsequent capacitor structure and adjacent devices.
In accordance with the present invention a method of fabricating a buried stack capacitor structure is described. After formation of silicon oxide filled, STI regions in a semiconductor substrate, a silicon dioxide pad layer is grown on regions of the semiconductor substrate not occupied by the STI regions. A well region, needed for logic applications, is formed in areas of the semiconductor substrate not occupied to the STI regions. A silicon nitride layer, and a silicon oxide layer are then deposited followed by a planarizing CMP procedure, exposing silicon nitride only on the top surface of the STI regions. Selective removal of the exposed portions of silicon nitride result in a planarized top surface featuring composite insulator regions comprised of silicon oxide-silicon nitride-silicon dioxide, located between STI regions. Photolithographic and selective dry etching procedures are used to define an initial self-aligned opening via removal an unprotected top portion of silicon oxide in the STI region, and via selective removal of an unprotected portion of the silicon oxide component of the composite insulator region, located adjacent to the STI region, resulting in exposure of a portion of the silicon nitride component of the composite insulator region. After removal of the masking photoresist shape selective etching procedures are used to remove the portions of silicon nitride and portions of the silicon dioxide pad layer, not covered by a silicon oxide shape which was defined during the initial self aligned opening, resulting in definition of a final self-aligned opening for a buried stack capacitor structure. The portion of the semiconductor substrate exposed in the buried stack capacitor opening, located adjacent to the partially etched STI region, was not damaged as a result of the selective etching procedures used for definition of the final self-aligned opening. After deposition of a first polysilicon layer a photoresist shape is formed in the final self-aligned, buried stack capacitor opening, protecting regions of first polysilicon layer from a CMP procedure used to remove portions of first polysilicon layer from the planarized top surface of the composite insulator region located between STI shapes, the region in which subsequent devices will be formed in, resulting in the definition of the storage node structure of the buried stack capacitor structure. Formation of a capacitor dielectric layer and deposition of a second polysilicon layer, is followed by a patterning procedure applied to the second polysilicon layer, and to the capacitor dielectric layer, resulting in a buried stack capacitor structure, in the final self-aligned opening, comprised of a top plate formed from second polysilicon layer, a capacitor dielectric layer, and the storage node structure defined from first polysilicon layer. The silicon dioxide pad layer protected portions of the underlying semiconductor substrate located between STI regions, from the final capacitor definition procedure.